1. Field of the Invention
This invention relates in general to the field of microelectronics, and more particularly to a technique for incorporating extended address modes into an existing microprocessor instruction set architecture.
2. Description of the Related Art
Since microprocessors were fielded in the early 1970's, their use has grown exponentially. Originally applied in the scientific and technical fields, microprocessor use has moved over time from those specialty fields into commercial consumer fields that include products such as desktop and laptop computers, video game controllers, and many other common household and business devices.
Along with this explosive growth in use, the art has experienced a corresponding technology pull that is characterized by an escalating demand for increased speed, expanded addressing capabilities, faster memory accesses, larger operand size, more types of general purpose operations (e.g., floating point, single-instruction multiple data (SIMD), conditional moves, etc.), and added special purpose operations (e.g., digital signal processing functions and other multi-media operations). This technology pull has resulted in an incredible number of advances in the art which have been incorporated in microprocessor designs such as extensive pipelining, super-scalar architectures, cache structures, out-of-order processing, burst access mechanisms, branch prediction, and speculative execution. Quite frankly, a present day microprocessor is an amazingly complex and capable machine in comparison to its 30-year-old predecessors.
But unlike many other products, there is another very important factor that has constrained, and continues to constrain, the evolution of microprocessor architecture. This factor—legacy compatibility—furthermore accounts for much of the complexity that is present in a modern microprocessor. For market-driven reasons, many producers have opted to retain all of the capabilities that are required to insure compatibility with older, so-called legacy application programs as new designs are provided which incorporate new architectural features.
Nowhere has this legacy compatibility burden been more noticeable than in the development history of x86-compatible microprocessors. It is well known that a present day virtual-mode, 32-/16-bit x86 microprocessor is still capable of executing 8-bit, real-mode, application programs which were produced during the 1980's. And those skilled in the art will also acknowledge that a significant amount of corresponding architectural “baggage” is carried along in the x86 architecture for the sole purpose of supporting compatibility with legacy applications and operating modes. Yet while in the past developers have been able to incorporate newly developed architectural features into existing instruction set architectures, the means whereby use of these features is enabled—programmable instructions—are becoming scarce. More specifically, there are no more “spare” instructions in certain instruction sets of interest that provide designers with a way to incorporate newer features into an existing architecture.
In the x86 instruction set architecture, for example, there are no remaining undefined 1-byte opcode states. All 256 opcode states in the primary 1-byte x86 opcode map are taken up with existing instructions. As a result, x86 microprocessor designers must presently make a choice to either provide new features or to retain legacy compatibility. If new programmable features are to be provided, then they must be assigned to opcode states in order for programmers to exercise those features. And if spare opcode states do not remain in an existing instruction set architecture, then some of the existing opcode states must be redefined to provide for specification of the new features. Thus, legacy compatibility is sacrificed in order to make way for new feature growth.
One area that continues to plague microprocessor designers concerns the amount of virtual memory that can be addressed by application programs. Early microprocessor designs provided for 8-bit addresses. Then, as application programs became more complex, the requirement to access larger areas of memory provided the momentum to increase the size of addresses to 16 bits, giving programmers the capability to access memory spaces up to 64 kilobytes (kB) in size. The incorporation of virtual memory techniques into the architecture of microprocessors has likewise extended the addressing boundaries experienced at the operating system level when several applications compete for memory resources. And while the amount of physical memory that can be accessed using virtual memory techniques is essentially unlimited, the amount of virtual memory that an application program can access is limited by address size, that is, the number of virtual address bits provided for by a particular microprocessor architecture.
The present state of the art in microprocessors for desktop/laptop computing applications provides for 32-bit virtual (or, linear) addresses, thus allowing programs to access up to 4 gigabytes (GB) of virtual memory space. The number of bits in a virtual address provided for in a particular microprocessor architecture is commonly referred to as an address mode. And to retain compatibility with legacy application programs, a present day desktop/laptop microprocessor provides programmers with the capability to operate in a 32-bit address mode, a 16-bit address mode, or even perhaps an 8-bit address mode.
But even at present, there are application programming areas that are disadvantageously impacted because present day microprocessors do not support extended address modes such as 64-bit data mode and 128-bit data mode. It is not uncommon to find image, signal, and multi-media applications that require access to arrays much greater than 4 GB in size. Yet, to support these extended addressing modes within an architecture that has no spare opcode values would require redefinition of existing opcodes, thereby abandoning support for legacy applications.
Therefore, what is needed is an apparatus and method that incorporate extended address modes into an existing microprocessor instruction set architecture having a completely full opcode set, where incorporation of the extended address modes additionally allows a conforming microprocessor to retain the capability to execute legacy application programs.